1. Technical Field of the Invention
The present invention relates to a field programmable device (FPD) and in particular but not exclusively to Field Programmable Gate Arrays (FPGA).
2. Description of Related Art
Programmable gate arrays (PGA) have dramatically changed the process of designing digital hardware over the last few years. Unlike previous generations of digital electronic technology, where board level designs included large numbers of integrated circuits containing basic gates, virtually every digital design produced today consists mostly of high density integrated circuit devices. This is applied not only to custom devices such as processing units and memory, but also to solid state machines such as controllers, counters, registers and decoders.
When such circuits are destined for high volume systems, they have been integrated into high density gate arrays. However, for prototyping or other low volume situations, many product designs are built using field programmable devices (FPD), one variant of which are field programmable gate arrays (FPGA). A field programmable device such as the FPGA is at its most basic level a series of configurable logic blocks (CLB), interconnected by a series of configurable connections or links, and read from and written to by a configurable input/output device.
The effectiveness of a field programmable device is the ability of the device to represent a required digital design, and be capable of being altered without the need for complete replacement. This ability is dependent on several factors such as device speed, and the complexity of design capable of being simulated. The complexity of the design is itself dependent on the complexity of the interconnections between the configurable logic blocks, and the number of the configurable logic blocks. The greater the number of blocks and the more complex the interconnection environment, the more complex the design that can be realized.
Interconnects are generally programmed, in the case of memory based FPDs, by a series of switching matrices controlled by memory latches. The memory latches create closed or open circuits between pairs of conducting lines. These configuration latches are supplied configuration data from a series of configuration registers and are enabled by an address register in a manner similar to the addressing and writing to a typical memory cell. The address and configuration data are passed to the configuration latches by a series of configuration and address lines.
In order to test that the configuration has been carried out successfully, a verification step is typically introduced after configuration and prior to using the device in an active mode. This verification step involves using a series of test input signals, or test vectors, and monitoring the output of the FPD. The output of the simulated circuit is checked against the test vector input to enable the verification step to determine if a configuration error has occurred and if enough test vectors are entered, the verification step may determine which region or which configuration latch has failed.
This verification step therefore increases the time spent in the configuration mode. Also should any errors be detected the device has to restart the whole configuration cycle again. Solutions for detecting an error in data stored in configuration SRAM and user assignable SRAM in a FPGA have been proposed. U.S. Pat. No. 6,237,124 describes such a method. This method, though, describes separate write and read phases. The write phase describes a method for writing to configuration SRAM and also using the same data into Cyclic Redundancy Check (CRC) circuitry. The read phase describes when data is read from the configuration SRAM and fed into the same CRC circuitry, then comparing the CRC values to determine if there is a fault. This method therefore requires two phases in order to perform a single test. In other words, a write phase is required to initiate the test followed by a read phase to trigger the test value. This test is also unable to determine the exact location of the fault.
Based upon the foregoing, there is a need for a field programmable device that is efficiently configured and verified.